SH7721 datasheet(314/1524 Pages) RENESAS

314 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 252 of 1458

REJ09B0033-0300

8.3.4

Interrupt Request Register 0 (IRR0)

IRR0 is an 8-bit register that indicates interrupt requests from the TMU and IRQ0 to IRQ5.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

TMU_

SUNIR

R/W

TMU_SUNI Interrupt Request

Indicates whether the TMU_SUNI (TMU) interrupt request

is generated.

0: TMU_SUNI interrupt request is not generated

1: TMU_SUNI interrupt request is generated

IRQ5R

IRQ4R

IRQ3R

IRQ2R

IRQ1R

IRQ0R

R/W

IRQn Interrupt Request

Indicates whether there is interrupt request input to the

IRQn pin. When edge-detection mode is set for IRQn, an

interrupt request is cleared by writing 0 to the IRQnR bit

after reading IRQnR = 1.

When level-detection mode is set for IRQn, these bits

indicate whether an interrupt request is input. The

interrupt request is set/cleared by only 1/0 input to the

IRQn pin.

IRQnR

0: No interrupt request input to IRQn pin

1: Interrupt request input to IRQn pin

[Legend] n = 0 to 5

SH7721 Datasheet(PDF) 314 Page - Renesas Technology Corp

SH7721 Datasheet(HTML) 314 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL