SH7721 datasheet(315/1524 Pages) RENESAS

315 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 253 of 1458

REJ09B0033-0300

8.3.5

Interrupt Request Register 1 (IRR1)

IRR1 is an 8-bit register that indicates whether interrupt requests from the DMAC are generated.

This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in

standby mode.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DEI3R

R/W

DEI3 Interrupt Request

Indicates whether the DEI3 (DMAC) interrupt is

generated.

0: DEI3 interrupt request is not generated

1: DEI3 interrupt request is generated

DEI2R

R/W

DEI2 Interrupt Request

Indicates whether the DEI2 (DMAC) interrupt

request is generated.

0: DEI2 interrupt request is not generated

1: DEI2 interrupt request is generated

DEI1R

R/W

DEI1 Interrupt Request

Indicates whether the DEI1 (DMAC) interrupt

request is generated.

0: DEI1 interrupt request is not generated

1: DEI1 interrupt request is generated

DEI0R

R/W

DEI0 Interrupt Request

Indicates whether the DEI0 (DMAC) interrupt

request is generated.

0: DEI0 interrupt request is not generated

1: DEI0 interrupt request is generated

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