SH7721 datasheet(319/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

319 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 257 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W

Description

TUNI0R

R/W

TUNI0 Interrupt Request

Indicates whether the TUNI0 (TMU) interrupt

request is generated.

0: TUNI0 interrupt request is not generated

1: TUNI0 interrupt request is generated

ITIR

R/W

ITI Interrupt Request

Indicates whether the ITI (WDT) interrupt request

is generated.

0: ITI interrupt request is not generated

1: ITI interrupt request is generated

2, 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

RCMIR

R/W

RCMI Interrupt Request

Indicates whether the RCMI (REF) interrupt

request is generated.

0: RCMI interrupt request is not generated

1: RCMI interrupt request is generated

8.3.9

Interrupt Request Register 5 (IRR5)

IRR5 is an 8-bit register that indicates whether interrupt requests from the SCIF0, SCIF1, DMAC,

and ADC are generated. This register is initialized to H'00 by a power-on reset or manual reset,

but is not initialized in standby mode.

SH7721 Datasheet(PDF) 319 Page - Renesas Technology Corp

SH7721 Datasheet(HTML) 319 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL