SH7721 datasheet(317/1524 Pages) RENESAS

317 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 255 of 1458

REJ09B0033-0300

8.3.7

Interrupt Request Register 3 (IRR3)

IRR3 is an 8-bit register that indicates whether interrupt requests from the RTC and SIM are

generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not

initialized in standby mode.

Bit

Bit Name

Initial Value

R/W

Description

TENDIR

R/W

TENDI Interrupt Request

Indicates whether the TENDI (SIM) interrupt is

generated.

0: TENDI interrupt request is not generated

1: TENDI interrupt request is generated

TXIR

R/W

TXI Interrupt Request

Indicates whether the TXI (SIM) interrupt request

is generated.

0: TXI interrupt request is not generated

1: TXI interrupt request is generated

RXIR

R/W

RXI Interrupt Request

Indicates whether the RXI (SIM) interrupt request

is generated.

0: RXI interrupt request is not generated

1: RXI interrupt request is generated

ERIR

R/W

ERI Interrupt Request

Indicates whether the ERI (SIM) interrupt request

is generated.

0: ERI interrupt request is not generated

1: ERI interrupt request is generated



Reserved

This bit is always read as 0. The write value should

always be 0.

CUIR

R/W

CUI Interrupt Request

Indicates whether the CUI (RTC) interrupt request

is generated.

0: CUI interrupt request is not generated

1: CUI interrupt request is generated

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