SH7721 datasheet(312/1524 Pages) RENESAS

312 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 250 of 1458

REJ09B0033-0300

8.3.3

Interrupt Control Register 1 (ICR1)

ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to

IRQ0 individually: rising edge, falling edge, high level, or low level.

Bit

Bit Name

Initial

Value

R/W

Description

MAI

R/W

All Interrupt Mask

When this bit is set to 1, all interrupt requests are masked

while low level is input to the NMI pin. The NMI interrupt

is masked in standby mode.

0: When the NMI pin is low, all interrupt requests are not

masked

1: When the NMI pin is low, all interrupt requests are

masked

IRQLVL

R/W

Interrupt Request Level Detection

Enables or disables the use of pins IRQ3 to IRQ0 as four

independent interrupt pins. The IRQ4 and IRQ5 are not

affected.

0: Use of pins IRQ3 to IRQ0 as four independent interrupt

pins enabled

1: Use of pins

IRL3 to IRL0 as encoded 15 level interrupt

pins

BLMSK

R/W

BL Bit Mask

When the BL bit in the SR register is set to 1, specifies

whether the NMI interrupt is masked.

0: When the BL bit is set to 1, the NMI interrupt is masked

1: The NMI interrupt is accepted regardless of the BL bit

setting

—

Reserved

This bit is always read as 0. The write value should

always be 0.

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