SH7721 datasheet(297/1524 Pages) RENESAS

297 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 235 of 1458

REJ09B0033-0300

Table 7.2

Instruction Positions and Restriction Types

Instruction

Position

SPC*

Illegal

Instruction*

Interrupt,

Break*

CPU Address

Error*

[A]

[B]

Retained

[C1]

Added

Retained

Instruction/data

[C2]

Illegal

Added

Retained

Instruction/data

Notes: 1. A specific address is specified in the SPC if an exception occurs while SR.RC[11:0]

≥ 2.

2. There are a greater number of instructions that can be illegal instructions while

SR.RC[11:0]

≥ 1.

3. An interrupt, break or DMA address error request is retained while SR.RC[11:0]

≥1.

4. A specific exception code is specified while SR.RC[11:0]

≥1.

• Example 1: Repeat loop consisting of four or greater instructions

LDRS RptStart

; [A]

LDRE RptDtct + 4

; [A]

SETRC #4

; [A]

instr0

; [A]

RptStart: instr1

; [A][Repeat start instruction]

………

; [A]

………

; [A]

RptDtct:

RptDtct

; [B] A repeat detection

instruction is an

instruction three

instructions before a

repeat end instruction

RptDtct1

; [C1]

RptDtct2

; [C2]

RptEnd:

RptDtct3

; [C2][Repeat end instruction]

instrNext

; [A]

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