Electronic Components Datasheet Search
  English  ▼

X  

SH7721 Datasheet(PDF) 294 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 294 Page - Renesas Technology Corp

Back Button SH7721 Datasheet HTML 290Page - Renesas Technology Corp SH7721 Datasheet HTML 291Page - Renesas Technology Corp SH7721 Datasheet HTML 292Page - Renesas Technology Corp SH7721 Datasheet HTML 293Page - Renesas Technology Corp SH7721 Datasheet HTML 294Page - Renesas Technology Corp SH7721 Datasheet HTML 295Page - Renesas Technology Corp SH7721 Datasheet HTML 296Page - Renesas Technology Corp SH7721 Datasheet HTML 297Page - Renesas Technology Corp SH7721 Datasheet HTML 298Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 294 / 1524 page
background image
Section 7 Exception Handling
Rev. 3.00 Jan. 18, 2008 Page 232 of 1458
REJ09B0033-0300
(2)
TLB invalid exception
• Conditions
Comparison of TLB addresses shows address match but V = 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'040
An exception occurred during write: H'060
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
(3)
TLB protection exception
• Conditions
When a hit access violates the TLB protection information (PR bits).
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'0A0
An exception occurred during write: H'0C0
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com