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SH7721 Datasheet(PDF) 294 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 294 Page - Renesas Technology Corp |
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294 / 1524 page ![]() Section 7 Exception Handling Rev. 3.00 Jan. 18, 2008 Page 232 of 1458 REJ09B0033-0300 (2) TLB invalid exception • Conditions Comparison of TLB addresses shows address match but V = 0. • Types Instruction synchronous, re-execution type • Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) • Exception code An exception occurred during read: H'040 An exception occurred during write: H'060 • Remarks The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is updated. (3) TLB protection exception • Conditions When a hit access violates the TLB protection information (PR bits). • Types Instruction synchronous, re-execution type • Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) • Exception code An exception occurred during read: H'0A0 An exception occurred during write: H'0C0 • Remarks The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is updated. |
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