SH7721 datasheet(291/1524 Pages) RENESAS

291 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 229 of 1458

REJ09B0033-0300

(3)

Illegal slot instruction

• Conditions

 When undefined code in a delay slot is decoded

Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

 When a privileged instruction in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR

with LDC/STC are not privileged instructions.

 When an instruction that rewrites PC in a delay slot is decoded

Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,

BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR

• Types

Instruction synchronous, re-execution type

• Save address

A delayed branch instruction address

• Exception code

H'1A0

• Remarks

None

(4)

Unconditional trap

• Conditions

TRAPA instruction executed

• Types

Instruction synchronous, processing-completion type

• Save address

An address of an instruction following TRAPA

• Exception code

H'160

• Remarks

The exception is a processing-completion type, so an instruction after the TRAPA instruction

is saved to SPC. The 8-bit immediate value in the TRAPA instruction is set in TRA[9:2].

SH7721 Datasheet(PDF) 291 Page - Renesas Technology Corp