SH7721 datasheet(289/1524 Pages) RENESAS

289 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 227 of 1458

REJ09B0033-0300

7.3

Individual Exception Operations

This section describes the conditions for specific exception handling, and the processor operations.

This section describes resets and general exceptions. For interrupt operations, refer to section 8,

Interrupt Controller (INTC).

7.3.1

Resets

(1)

Power-On Reset

• Conditions

Power-on reset is request

• Operations

Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the

reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.

(2)

Manual Reset

• Conditions

Manual reset is request

• Operations

Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the

reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.

7.3.2

General Exceptions

(1)

CPU address error

• Conditions

 Instruction is fetched from odd address (4n + 1, 4n + 3)

 Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)

 Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,

4n + 3)

 The area ranging from H'80000000 to H'FFFFFFFF in virtual space is accessed in user

mode

• Types

Instruction synchronous, re-execution type

SH7721 Datasheet(PDF) 289 Page - Renesas Technology Corp