SH7721 datasheet(286/1524 Pages) RENESAS

286 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 224 of 1458

REJ09B0033-0300

unconditional delayed branch instruction or an instruction following a conditional delayed branch

instruction whose branch condition is satisfied. If a branch does not occur in a conditional delayed

branch, the normal processing is executed.

(3)

Acceptance Priority and Test Priority

Acceptance priorities are determined for all exception requests. The priority of resets, general

exceptions, and interrupts are determined in this order: a reset is always accepted regardless of the

CPU status. Interrupts are accepted only when resets or general exceptions are not requested.

If multiple general exceptions occur simultaneously in the same instruction, the priority is

determined as follows.

A processing-completion type exception generated at the previous instruction*

A user break before instruction execution (re-execution type)

An exception related to an instruction fetch (CPU address error and MMU related exceptions:

re-execution type)

An exception caused by an instruction decode (General illegal instruction exceptions and slot

illegal instruction exceptions: re-execution type, unconditional trap: processing-completion

type)

An exception related to data access (CPU address error and MMU related exceptions: re-

execution type)

Unconditional trap (processing-completion type)

A user break other than one before instruction execution (processing-completion type)

DMA address error (processing-completion type)

Note: * If a processing-completion type exception is accepted at an instruction, exception

processing starts before the next instruction is executed. This exception processing

executed before an exception generated at the next instruction is detected.

Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all

exception requests being processed.

SH7721 Datasheet(PDF) 286 Page - Renesas Technology Corp