SH7721 datasheet(287/1524 Pages) RENESAS

287 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 225 of 1458

REJ09B0033-0300

Table 7.1

Exception Event Vectors

Exception

Type

Current

Instruction

Exception Event

Priority*

Exception

Order

Process

at BL=1

Vector

Code

Vector

Offset

Power-on reset

Reset

H'000

—

Reset

(asynchro-

nous)

Aborted

Manual reset

Reset

H'020

—

User break(before

instruction execution)

Ignored

H'1E0

H'00000100

CPU address error

(instruction access) *

Reset

H'0E0

H'00000100

TLB miss

(instruction access) *

4*5

1-1

Reset

H'040

H'00000400

TLB invalid (instruction

access)*

4*5

1-2

Reset

H'040

H'00000100

TLB protection violation

(instruction access)*

4*5

1-3

Reset

H'0A0

H'00000100

Illegal general instruction

exception

Reset

H'180

H'00000100

Illegal slot

instruction exception

Reset

H'1A0

H'00000100

CPU address error

(data access)*

Reset

H'0E0/

H'100

H'00000100

Re-executed

TLB miss

(data access)*

4*5

3-1

Reset

H'040/

H'060

H'00000400

TLB invalid

(data access)*

4*5

3-2

Reset

H'040/

H'060

H'00000100

TLB protection violation

(data access)*

4*5

3-3

Reset

H'0A0/

H'0C0

H'00000100

Re-executed

Initial page write

(data access)*

4*5

3-4

Reset

H'080

H'00000100

Unconditional trap

(TRAPA instruction)

Reset

H'160

H'00000100

General

exception

events

(synchro-

nous)

Completed

User breakpoint (After

instruction execution,

address)

Ignored

H'1E0

H'00000100

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