SH7721 datasheet(290/1524 Pages) RENESAS

290 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 228 of 1458

REJ09B0033-0300

• Save address

Instruction fetch: An instruction address to be fetched when an exception occurred

Data access: An instruction address where an exception occurs (a delayed branch instruction

address if an instruction is assigned to a delay slot)

• Exception code

An exception occurred during read: H'0E0

An exception occurred during write: H'100

• Remarks

The virtual address (32 bits) that caused the exception is set in TEA.

(2)

Illegal general instruction exception

• Conditions

 When undefined code not in a delay slot is decoded

Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

Note:

For details on undefined code, refer to table 2.12. When an undefined code other than

H'F000 to H'FFFF is decoded, operation cannot be guaranteed.

 When a privileged instruction not in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR

with LDC/STC are not privileged instructions.

• Types

Instruction synchronous, re-execution type

• Save address

An instruction address where an exception occurs

• Exception code

H'180

• Remarks

None

SH7721 Datasheet(PDF) 290 Page - Renesas Technology Corp