SH7721 datasheet(292/1524 Pages) RENESAS

292 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 230 of 1458

REJ09B0033-0300

(5)

User break point trap

• Conditions

When a break condition set in the user break controller is satisfied

• Types

Break (L bus) before instruction execution: Instruction synchronous, re-execution type

Operand break (L bus): Instruction synchronous, processing-completion type

Data break (L bus): Instruction asynchronous, processing-completion type

I bus break: Instruction asynchronous, processing-completion type

• Save address

Re-execution type: An address of the instruction where a break occurs (a delayed branch

instruction address if an instruction is assigned to a delay slot)

Processing-completion type: An address of the instruction following the instruction where a

break occurs (a delayed branch instruction destination address if an instruction is assigned to a

delay slot)

• Exception code

H'1E0

• Remarks

For details on user break controller, refer to section 33, User Break Controller (UBC).

(6)

DMA address error

• Conditions

 Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)

 Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +

• Types

Instruction asynchronous, processing-completion type

• Save address

An address of the instruction following the instruction where a break occurs (a delayed branch

instruction destination address if an instruction is assigned to a delay slot)

• Exception code

H'5C0

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