SH7721 datasheet(296/1524 Pages) RENESAS

296 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 234 of 1458

REJ09B0033-0300

7.4

Exception Processing While DSP Extension Function is Valid

When the DSP extension function is valid (the DSP bit in SR is set to 1), some exception

processing acceptance conditions or exception processing may be changed.

7.4.1

Illegal Instruction Exception and Illegal Slot Instruction Exception

In the DSP mode, a DSP extension instruction can be executed. If a DSP extension instruction is

executed when the DSP bit in SR is cleared to 0 (in a mode other than the DSP mode), an illegal

instruction exception occurs.

In the DSP mode, STC and LDC instructions for the SR register can be executed even in user

mode. (Note, however, that only the RC[11:0], DMX, DMY, and RF[1:0] bits in the DSP

extension bits can be changed.)

7.4.2

CPU Address Error

In the DSP mode, a part of the space P2 (Uxy area: H'A5000000 to H'A5FFFFFF) can be accessed

in user mode and no CPU address error will occur even if the area is accessed.

7.4.3

Exception in Repeat Control Period

If an exception is requested or an exception is accepted during repeat control, the exception may

not be accepted correctly or a program execution may not be returned correctly from exception

processing that is different from the normal state. These restrictions may occur from repeat

detection instruction to repeat end instruction while the repeat counter is 1 or more. In this section,

this period is called the repeat control period.

The following shows program examples where the number of instructions in the repeat loop are 4

or more, 3, 2, and 1, respectively. In this section, a repeat detection instruction and its instruction

address are described as RptDtct. The first, second, and third instructions following the repeat

detection instruction are described as RptDtct1, RptDtct2, and RptDtct3. In addition, [A], [B],

[C1], and [C2] in the following examples indicate instructions where a restriction occurs. Table

7.2 summarizes the instruction positions and restriction types.

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