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SH7721 Datasheet(PDF) 295 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 295 Page - Renesas Technology Corp

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Section 7 Exception Handling
Rev. 3.00 Jan. 18, 2008 Page 233 of 1458
REJ09B0033-0300
(4)
Initial page write exception
• Conditions
A hit occurred to the TLB for a store access, but D
= 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
H'080
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.



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