SH7721 datasheet(283/1524 Pages) RENESAS

283 / 1524 page

Section 7 Exception Handling

Rev. 3.00 Jan. 18, 2008 Page 221 of 1458

REJ09B0033-0300

7.2

Exception Handling Function

7.2.1

Exception Handling Flow

In exception handling, the contents of the program counter (PC) and status register (SR) are saved

in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of

the exception handler is invoked from a vector address. By executing the return from exception

handler (RTE) in the exception handler routine, it restores the contents of PC and SR, and returns

to the processor state at the point of interruption and the address where the exception occurred.

A basic exception handling sequence consists of the following operations. If an exception occurs

and the CPU accepts it, operations 1 to 8 are executed.

The contents of PC is saved in SPC.

The contents of SR is saved in SSR.

The block (BL) bit in SR is set to 1, masking any subsequent exceptions.

The mode (MD) bit in SR is set to 1 to place the privileged mode.

The register bank (RB) bit in SR is set to 1.

An exception code identifying the exception event is written to bits 11 to 0 of the exception

event register (EXPEVT); an exception code identifying the interrupt request is written to bits

11 to 0 of the interrupt event register (INTEVT) or interrupt event register 2 (INTEVT2).

If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA

instruction is set to TRA. For an exception related to memory accesses, the logic address

where the exception occurred is written to TEA.*

Instruction execution jumps to the designated exception vector address to invoke the handler

routine.

The above operations from 1 to 8 are executed in sequence. During these operations, no other

exceptions may be accepted unless multiple exception acceptance is enabled.

In an exception handling routine for a general exception, the appropriate exception handling must

be executed based on an exception source determined by the EXPEVT. In an interrupt exception

handling routine, the appropriate exception handling must be executed based on an exception

source determined by the INTEVT or INTEVT2. After the exception handling routine has been

completed, program execution can be resumed by executing an RTE instruction. The RTE

instruction causes the following operations to be executed.

SH7721 Datasheet(PDF) 283 Page - Renesas Technology Corp