 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SH7721 Datasheet(PDF) 282 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7721 Datasheet(HTML) 282 Page - Renesas Technology Corp |
|
|
282 / 1524 page  Section 7 Exception Handling Rev. 3.00 Jan. 18, 2008 Page 220 of 1458 REJ09B0033-0300 7.1.4 Interrupt Event Register 2 (INTEVT2) INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified using the software. Bit Bit Name Initial Value R/W Description 31 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 INTEVT2 R 12-bit Exception Code 7.1.5 Exception Address Register (TEA) TEA is assigned to address H'FFFFFFFC and the virtual address for an exception occurrence is stored in this register when an exception related to memory accesses occurs. TEA can be modified using the software. Bit Bit Name Initial Value R/W Description 31 to 0 TEA All 0 R/W The virtual address for an exception occurrence |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
