SH7721 datasheet(278/1524 Pages) RENESAS

278 / 1524 page

Section 6 X/Y Memory

Rev. 3.00 Jan. 18, 2008 Page 216 of 1458

REJ09B0033-0300

6.3.3

MMU and Cache Settings

When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct

operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled

(CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. If

the X/Y memory is accessed from space P0, P3, or U0, it is advisable to access the X/Y memory

via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and

cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus,

several cycles are necessary (the number of necessary cycles varies according to the ratio between

the internal clock (I

φ) and bus clock (Bφ) or the operation state of the DMAC). In a program that

requires high performance, it is advisable to access the X/Y memory from space P2 or Uxy. The

relationship described above is summarized in table 6.2.

Table 6.2

MMU and Cache Settings

Setting

Virtual Address Space and Access Enabled or Disabled

CCR1.CE

MMUCR.AT

P0, U0

P2, Uxy

Note:

A: Accessible (recommended)

B: Accessible

C: Accessible (Note that MMU page attribute must be specified as cache disabled by

clearing the C bit to 0.)

X: Not accessible

6.3.4

Sleep Mode

In sleep mode, I bus master modules such as the DMAC cannot access the X/Y memory.

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