7477 datasheet(137/354 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

1-120

HARDWARE

1.13 Serial I/O

q Transmit interrupt operation (valid when the Serial I/O is selected)

Regarding a transmit interrupt, interrupt request generating timing can be selected by bit 3 of the

Serial I/O control register (SIOCON).

0: When the Transmit buffer register becomes empty after the data written in the Transmit buffer

1: When the shift operation of the Transmit shift register is completed, an interrupt request is

generated.

* In case of the UART, an interrupt operation is performed in the same way as when the synchronous

clock is selected.

Figure 1.13B.9 shows a transmit operation of UART and Figure 1.13B.10 shows a transmit timing

of UART.

Fig. 1.13B.9 Transmit operation of UART

P15/TxD

Data bus

Address 00E016

Write transmit data

Transmit buffer register

Serial I/O status register

(Address 00E116)

Transmit buffer register

Transmit shift register

Transfer transmit data

Serial I/O status register

(Address 00E116)

When “0” is selected by the bit 3

of the Serial I/O control register

Interrupt request register 1

(Address 00FC16)

Synchronous clock

Transmit shift register

Serial I/O status register

(Address 00E116)

Synchronous clock

Serial I/O status register

(Address 00E116)

When “1” is selected by the bit 3

of the Serial I/O control register

Interrupt request

(Address 00FC16)

Transmit shift register

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