7477 datasheet(145/354 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

1-128

HARDWARE

1.13 Serial I/O

1.13B.3 Notes on use

(1) Notes on external clock selection

In the 7477/7478 group, either the internal clock or external clock can be selected as the synchronous

clock. When the external clock is selected as the synchronous clock, take the following points into

consideration.

2 Clock synchronous serial I/O

1 During data transmission, when setting the transmit enable bit to “1” or writing data into the

Transmit buffer register, perform a write operation while the synchronous clock is at “H.”

2 The transmission or the shift operation of the Receive shift register is continued while the

synchronous clock is input to the serial I/O circuit. When the external clock is selected, stop the

synchronous clock at the end of 8 cycles. When the internal clock is selected, the synchronous

clock stops automatically at the end of 8 cycles.

3 When the external clock is selected, set the “H” and “L” widths (TWH, TWL) of the pulse used

as the external clock source to TWH, TWL [s]

Q 8/(f(XIN) [Hz]). For example, when f(XIN) is 8

MHz, use a clock of 500 kHz or less (duty ratio 50 %).

2 UART

Set the “H” and “L” widths (T WH, TWL) of the pulse used as the external clock source to TWH,

TWL [s]

Q 2/(f(XIN) [Hz]). For example, when f(XIN) is 8 MHz, use a clock of 2 MHz or

less (duty ratio 50 %).

__________

(2) When the SRDY output is performed in the clock synchronous serial I/O

__________

When the receive side using the external clock performs an SRDY output, set the receive enable bit,

__________

the SRDY output enable and the transmit enable bit to “1” (transmit enable).

(3) When a serial I/O transmit interrupt or a serial I/O receive interrupt is caused

2 When using a serial I/O transmit interrupt

1 Clear the serial I/O transmit interrupt request bit (bit 6 of IR1) to “0” after one instruction or

more after setting a value in the Serial I/O control register.

2 After setting in 1, set the serial I/O transmit interrupt enable bit (bit 6 of IE1) to “1.”

2 When using a serial I/O receive interrupt

1 Clear the serial I/O receive interrupt request bit (bit 5 of IR1) to “0” after one instruction or more

after setting a value in the Serial I/O control register.

2 After setting in 1, set the serial I/O receive interrupt enable bit (bit 5 of IE1) to “1.”

(4) Transmit interrupt request in the transmit enable state

After the transmit enable bit is set to “1,” the transmit buffer empty flag and the transmit shift

completion flag are set to “1.” Accordingly, even if a transmit buffer empty state is selected or a

termination of shift operation of the Transmit shift register is selected as a transmit interrupt source,

an interrupt request is generated and the transmit interrupt request bit is set to “1.”

For this reason, when using a transmit interrupt, set the transmit enable bit to “1,” clear the transmit

interrupt request bit to “0,” and then set the transmit interrupt enable bit to “1” (enable state).

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