7477 datasheet(146/354 Pages) RENESAS

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1-129

7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.13 Serial I/O

(5) Disabling transmission after transmission of 1-byte data

In the 7477/7478 group, it is possible to make reference to the transmit shift register completion flag

(TSC flag) to know that data has been transmitted.

The TSC flag is “0” during data transmission, and becomes “1” after data has been transmitted.

Accordingly, if data transmission is disabled at the time of confirmation of a change of the TSC flag

from “0” to “1,” data transmission can be terminated after 1-byte data is transmitted. However, the

TSC flag is also set to “1” when the serial I/O is enabled and does not become “0” until a synchronous

clock is generated and transmitted. For this reason, if data transmission is disabled by making

reference to the TSC flag at this time, data is not transmitted. Make reference to the TSC flag after

a start of data transmission.

The change of the TSC flag from “1” to “0” has a delay of 0.5 to 1.5 cycles of the synchronous clock.

(6) Re-setting the Serial I/O control register (SIOCON)

Re-set the Serial I/O control register after setting both transmit enable bit and receive enable bit to

“0” to re-set the transmit circuit and the receive circuit.

1 Clear both transmit enable bit (TE) and receive enable bit (RE) to “0.”

2 Set the bit 0 to bit 3 and bit 6 of the Serial I/O control register.

3 Set both transmit enable bit (TE) and receive enable bit (RE) to “1.”

(It is possible to set

2 and 3 simultaneously with the LDM instruction.)

(7) Stopping data transmit/receive

2 In the following cases, clear the transmit enable bit to “0” (transmit disable).

q To stop the transmit operation when data is transmitted in the clock synchronous serial I/O

q To stop the transmit operation when UART data is transmitted

q To stop only the transmit operation when UART data is transferred

2 In the following cases, clear receive enable bit (receive disable) or serial I/O enable bit to “0”

(serial I/O disable).

q To stop the receive operation when data is received in the clock synchronous serial I/O

2 In the following cases, clear the receive enable bit to “0.”

q To stop the receive operation when UART data is received.

q To stop only the receive operation when UART data is transferred.

2 In the following cases, clear both transmit enable bit and receive enable bit to “0” (transfer

disable) simultaneously.

q To stop the transmit operation and the receive operation when data is transferred in the clock

synchronous serial I/O

Note: When data is transferred in the clock synchronous serial I/O, it is impossible to stop only

the transmit operation or the receive operation.

7477 Datasheet(PDF) 146 Page - Renesas Technology Corp