7477 datasheet(150/354 Pages) RENESAS

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1-133

7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.13 Serial I/O

Each bit of the Serial I/O status register is described below.

2 Transmit buffer empty flag (TBE, bit 0)

This flag indicates the state of the Transmit buffer register.

This bit is set to “1” after the data written in the Transmit buffer register is transferred to the

Transmit shift register, and cleared to “0” after data is written into the Transmit buffer register.

This flag is valid in both clock synchronous serial I/O and UART.

2 Receive buffer full flag (RBF, bit 1)

This flag indicates the state of the Receive buffer register.

When 1-byte data has been all input to the Receive shift register and then the receive data has

been transferred from the Receive shift register to the Receive buffer register, this flag is automatically

set to “1.” When the transferred data has been read out from the Receive buffer register, the flag

is automatically cleared to “0.”

If receive data is further input to the Receive shift register when the receive buffer full flag is “1”

(without reading out the contents of the Receive buffer register), the overrun error flag is set to

“1.”

The receive buffer full flag is valid in both clock synchronous serial I/O and UART.

2 Transmit shift completion flag (TSC, bit 2)

This flag indicates the state of the transmit shift operation.

When transmit data has been transferred to the Transmit shift register and then a shift operation

has been started with the synchronous clock (transmission of the 1st bit of the transmit data), this

flag is cleared to “0.” When the shift operation has been completed (completion of transmission

the last bit of the transmit data), the flag is set to “1.”

This flag is valid in both clock synchronous serial I/O and UART.

2 Overrun error flag (OE, bit 3)

This flag indicates the receive data read state.

If receive data is further input to the Receive shift register when the receive buffer full flag is “1”

(without reading out the contents of the Receive buffer register), the overrun error flag is set to

“1.”

This flag is cleared to “0” by any operation shown in Table 1.13B.8.

This flag is valid in both clock synchronous Serial I/O and UART.

2 Parity error flag (PE, bit 4)

This flag indicates a hardware check result on the even parity or odd parity in the UART.

If there is a difference between the parity of received data and the set parity, the flag is set to

“1.”

This flag is cleared to “0” by any operation shown in Table 1.13B.8.

This flag is valid in the parity enable state in UART.

2 Framing error flag (FE, bit 5)

This flag judges a frame synchronization error in UART.

When the stop bit of receive data cannot be received at the set timing, the flag is set to “1.”

At stop bit detection, only the 1st stop bit is detected but the 2nd stop bit is not checked.

This flag is cleared by any operation shown in Table 1.13B.8.

This flag is valid in UART only.

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