7477 datasheet(154/354 Pages) RENESAS

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1-137

7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.13 Serial I/O

2 Receive enable bit (bit 5)

This bit controls the receive operation.

q When the serial I/O enable bit (bit 7) is “1” (serial I/O enable), the control shown in Table

1.13B.10 is exerted.

q When the serial I/O enable bit (bit 7) is “0” (serial I/O disable), this bit is invalid.

Table 1.13B.10 Receive enable bit function

∗1: Bit 1 of Serial I/O status register

∗2: Bit 3,4,5 and 6 of Serial I/O status register

2 Serial I/O mode selection bit (bit 6)

This bit selects the clock synchronous serial I/O or the UART.

• “0”: UART

• “1”: Clock synchronous serial I/O

2 Serial I/O enable bit (bit 7)

__________

This bit selects whether each of the P14/RxD, P15/TxD, P16/SCLK and P17/SRDY pins is used as

a port or a serial I/O pin.

When using the serial I/O, set this bit to “1.”

• “0”: The respective pins become P14 to P17.

__________

• “1”: The respective pins become serial I/O pins, RXD, TxD, SCLK, SRDY.

Note: In the UART, when the internal clock is selected, the P16/SCLK pin can be used as port P16.

__________

However, for the P17/SRDY pin, take the following points into consideration.

2 In the clock asynchronous serial I/O

__________

When using the P17/SRDY pin as serial I/O pin SRDY, set the SRDY output enable bit (bit 2) to “1.”

2 In the UART

__________

The P17/SRDY pin is used as P17 regardless of the value of the serial I/O enable bit.

Receive enable bit

Receive buffer full flag∗1

Cleared to “0”

Flag function is valid.

Each error flag∗2

Cleared to “0”

Flag function is valid.

P14/RXD pin function

Port P14

Serial I/O data transmit pin RXD

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