7477 datasheet(153/354 Pages) RENESAS

153 / 354 page

7470/7471/7477/7478 GROUP USER’S MANUAL

1-136

HARDWARE

1.13 Serial I/O

Each bit of the Serial I/O control register is described below.

2 BRG count source selection bit (CSS, bit 0)

This bit selects a count source to be input to the BRG.

• “0”: f(XIN)/4

• “1”: f(XIN)/16

2 Serial I/O synchronous clock selection bit (SCS, bit 1)

This bit selects a synchronous clock to be used for the serial I/O.

q In the clock synchronous serial I/O

• “0”: The BRG output divided by 4 becomes a shift clock.

• “1”: The external clock (P16/SCLK pin input) becomes a synchronous clock.

q In the UART

• “0”: The BRG output divided by 16 becomes a shift clock.

• “1”: The external clock (P16/SCLK pin input) divided by 16 becomes a synchronous clock.

__________

SRDY

output enable bit (SRDY, bit 2)

__________

This bit selects whether the P17/SRDY pin is used as P17 or as serial I/O pin SRDY or SRDY output

disable.

q In the clock synchronous serial I/O

__________

• “0”: SRDY pin output disable (used as port P17)

__________

• “1”: SRDY pin output enable (used as serial I/O pin SRDY)

q In the UART

__________

The P17/SRDY pin is used as P17 regardless of the value of this bit.

2 Transmit interrupt request selection bit (TIC, bit 3)

This bit determines a source for generating a transmit interrupt request.

• “0”: When the contents of the Transmit buffer register are transferred to the Transmit shift

• “1”: When the shift operation of the Transmit shift register terminates, a transmit interrupt

request is generated.

2 Transmit enable bit (TE, bit 4)

This bit controls a transmit operation.

q When the serial I/O enable bit (bit 7) is “0” (serial I/O disable)

The transmit enable bit is invalid.

q When the serial I/O enable bit (bit 7) is “1” (serial I/O disable)

The control shown in Table 1.13B.9 is exerted.

∗1: Bit 0 of Serial I/O status register

∗2: Bit 2 of Serial I/O status register

Transmit enable bit

Transmit buffer

empty flag∗1

Cleared to “0”

Flag function is valid.

Transmit shift

completion flag∗2

Cleared to “0”

Flag function is valid.

P15/TXD pin function

Port P15

Serial I/O data transmit pin TXD

Table 1.13B.9 Transmit enable bit function

7477 Datasheet(PDF) 153 Page - Renesas Technology Corp

7477 Datasheet(HTML) 153 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL