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AD7879 Datasheet(PDF) 4 Page - Analog Devices |
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AD7879 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 36 page ![]() AD7879 Rev. 0 | Page 4 of 36 SPI TIMING SPECIFICATIONS (AD7879) TA = −40°C to +85°C; VCC = 1.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.4 V. Table 2. Parameter1 Limit at TMIN, TMAX Unit Description fSCLK 5 MHz max t1 5 ns min CS falling edge to first SCL falling edge t2 20 ns min SCL high pulse width t3 20 ns min SCL low pulse width t4 15 ns min DIN setup time t5 15 ns min DIN hold time t6 20 ns max DOUT access time after SCL falling edge t7 16 ns max CS rising edge to DOUT high impedance t8 15 ns min SCL rising edge to CS high 1 Guaranteed by design, not production tested. CS SCL DIN DOUT t1 116 15 MSB LSB 23 MSB LSB 12 15 16 t2 t4 t5 t3 t6 t7 t8 Figure 2. Detailed SPI Timing Diagram |
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