AD7879

Rev. 0 | Page 32 of 36

DIN

CW

15

CW

14

CW

13

CW

8

CW

1

CW

0

XX

SCL

CW

12

XX

XX

X

READBACK DATA FOR

STARTING REGISTER ADDRESS

X

X

1

32

2

3

4

15

16

17

18

31

34

33

48

47

49

CS

CW

11

CW

10

CW

9

CW

7

CW

2

CW

6

CW

5

CW

4

CW

3

11

12

13

14

5678

910

XXX XXX XXX

XXX

D15

D14

D1

D0

D1

D0

D15

D15

D14

XXX XXX XXX XXX XXX XXX XXX

XXX XXX

XXX

XXX XXX

DOUT

16-BIT COMMAND WORD

ENABLE WORD

R/W

REGISTER ADDRESS

NOTES

1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY.

2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDA: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.

3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDA PIN.

4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.

5. X DENOTES DON’T CARE.

6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.

7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:

CW[15:11] = 11100 (ENABLE WORD)

CW[10] = 1 (R/W)

CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)

READBACK DATA FOR

NEXT REGISTER ADDRESS

Figure 41. Sequential Register Read Back SPI Timing

the SCL and SDA inputs. The SDA is an I/O pin that allows both

register write and register read back operations. The AD7879-1 is

It has a 7-bit device address, Address 0101 1XX. The lower two

bits are set by tying the ADD0 and ADD1 pins high or low. The

AD7879-1 responds when the master device sends its device

address over the bus. The AD7879-1 cannot initiate data transfers

on the bus.

ADD1

ADD0

0

0

0101 100

0

1

0101 101

1

0

0101 110

1

1

0101 111

Data Transfer

master initiates a data transfer by establishing a start condition,

defined as a high-to-low transition on the serial data line, SDA,

while the serial clock line, SCL, remains high. This indicates

that an address/data stream follows.

All slave peripherals connected to the serial bus respond to the

start condition and shift in the next eight bits, consisting of a

7-bit address (MSB first) plus an R/W bit that determines the

direction of the data transfer. The peripheral whose address

corresponds to the transmitted address responds by pulling the

data line low during the ninth clock pulse. This is known as the

acknowledge bit. All other devices on the bus then remain idle

while the selected device waits for data to be read from, or

written to it. If the R/W bit is a 0, the master writes to the slave

device. If the R/W bit is a 1, the master reads from the slave

device.

Data is sent over the serial bus in a sequence of nine clock

pulses (eight bits of data followed by an acknowledge bit from

the slave device). Transitions on the data line must occur during

the low period of the clock signal and remain stable during the

high period, because a low-to-high transition when the clock

is high can be interpreted as a stop signal. The number of data

bytes transmitted over the serial bus in a single read or write

operation is limited only by what the master and slave devices

can handle.

When all data bytes are read or written, a stop condition is

established. A stop condition is defined by a low-to-high

transition on SDA while SCL remains high. If the AD7879

encounters a stop condition, it returns to its idle condition.