AD7879

Rev. 0 | Page 33 of 36

NOTES

1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH.

2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH.

3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE Xs ARE DON'T CARE BITS.

4. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.

SDA

DEV

A6

DEV

A5

DEV

A4

R/W

SCL

DEV

A3

123

4

17

DEV

A2

DEV

A1

DEV

A0

ACK

A7

A6

11

16

56

78

910

START

AD7879 DEVICE ADDRESS

A1

A0

REGISTER ADDRESS[A7:A0]

D15

D14

D9

D8

26

18

19

20

25

28

27

34

29

35

D1

D0

D7

D6

REGISTER DATA[D15:D8 ]

REGISTER DATA[D7:D0]

ACK

ACK

36

37

ACK

STOP

DEV

A6

DEV

A5

DEV

A4

123

START

AD7879 DEVICE ADDRESS

shown in Figure 42 and Figure 44. The device address is sent

over the bus followed by the R/W bit set to 0. This is followed

by two bytes of data that contain the 10-bit address of the inter-

nal data register to be written. The address is contained in the

8 LSBs of the register address byte. The bit map in

shows the register address byte.

Table 24

Table 24.

MSB

LSB

7

6

5

4

3

2

1

0

Register Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

The third data byte contains the 8 MSBs of the data to be

written to the internal register. The fourth data byte contains

the 8 LSBs of data to be written to the internal register.

The AD7879-1 address pointer register automatically increments

after each write. This allows the master to sequentially write to all

registers on the AD7879-1 in the same write transaction. However,

the address pointer register does not wrap around after the last

address.

Any data written to the AD7879-1 after the address pointer has

reached its maximum value is discarded.

All registers on the AD7879-1 have 16 bits. Two consecutive

8-bit data bytes are combined and written to the 16-bit registers.

To avoid errors, all writes to the device must contain an even

number of data bytes.

To finish the transaction, the master generates a stop condition

on SDA, or generates a repeat start condition if the master is to

maintain control of the bus.

To read from the AD7879-1, the address pointer register must

first be set to the address of the required internal register. The

master performs a write transaction and writes to the AD7879-1

to set the address pointer. The master then outputs a repeat start

condition to keep control of the bus, or if this is not possible, the

master ends the write transaction with a stop condition. A read

transaction is initiated, with the R/W bit set to 1.

The AD7879-1 supplies the upper eight bits of data from the

addressed register in the first read back byte, followed by the

lower eight bits in the next byte. This is shown in Figure 43

and Figure 44.

Because the address pointer automatically increases after each

read, the AD7879-1 continues to output readback data until

the master puts a no acknowledge and a stop condition on the

bus. If the address pointer reaches its maximum value, and the

master continues to read from the part, the AD7879-1 repeat-

edly sends data from the last register addressed.