AD7879 datasheet(28/36 Pages) AD

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AD7879

Rev. 0 | Page 28 of 36

AVG

FINISHED?

FCD

REQ’D?

MAV FILTER

ENABLED

START ACQUIST TIMER

AND WAIT FOR

ACQUISITION

CONVERT: WAIT FOR

DATA_READY

RUN

AVERAGER

TXFER DATA

TO REG. MAP

SET CHANNEL

CONV_START = 1

CONV_START = 0

MEDIAN

WINDOW

FINISHED?

COMPARE NEW

READING

SHIFT

READINGS

RUN FILTER

AVERAGER

OUT-OF-

LIMIT?

LIMIT

COMPARISON

NO FCD

REQ’D

SET ALERT AND

INTERRUPT

EOCS

YES

START FCD

TIMER

WAIT FOR

FCD

YES

END OF

CONVERSION

SEQUENCE

YES

NOTE THAT CONVERSION

SEQUENCE MAY BE 1

CHANNEL ONLY (MODE 01).

START OF

CONVERSION

SEQUENCE

Figure 33. Conversion Sequence

INTERRUPTS

The AD7879 has a dual function interrupt output, INT, as well

as a pen down interrupt, PENIRQ. The INT output can be con-

figured as a data available interrupt, as an out of limit interrupt, or

as a GPIO interrupt.

INT—Data Available

The behavior of the interrupt output is controlled by Bit 13 in

Control Register 3. In default mode, INT operates as a data

available interrupt (Bit 13 = 0). When the AD7879 has finished

a conversion or a conversion sequence, the interrupt asserts to

let the host know that new ADC data is available in the result

registers.

While the ADC is idle or is converting, INT is high. When the

ADC has finished converting and new data has been written to

the results registers, INT goes low. Reading the result registers

resets INT to a high condition. INT is also reset if a new conver-

sion is started by the AD7879 because the timer expired. The

host should read the results registers only when INT is low. To

ensure correct operation of the DAV mode when using the SPI

interface it is necessary to write 0x0000 to Register 0x81 after a

set of register reads. This clears the internal data read signal.

ADC

CONVERTING

SETUP

BY HOST

IDLE

NEW DATA

AVAILABLE

HOST READS

RESULTS

IDLE

tCONV

AD7879

STATUS

INT

Figure 34. Operation of INT Output

When the on-board timer is programmed to perform automatic

conversions, limited time is available to the host to read the

results registers before another sequence of conversions begins.

The INT signal is reset high when the timer expires, and the

host should not access the results registers while INT is high.

INT—Out of Limits

The INT pin operates as an alarm or interrupt output when

Bit 13 in Register 0x03 is set to 1. The output goes low if any

one of the interrupt sources is asserted. The results of high and

low limit comparisons on the AUX, VBAT, and TEMP channels

are interrupt sources. An out-of-limit comparison sets a status

bit in the interrupt register. There are separate status bits for

both the high and low limits on each channel to indicate which

limit was exceeded. The interrupt sources can be masked by

clearing the corresponding enable bit in this register. There is

one enable bit per channel.

PENIRQ— Pen Interrupt

The pen interrupt request output (PENIRQ) goes low when-

ever the screen is touched and the PENIRQ enable bit is set to

0 (Control Register 1, Bit 15). When PENIRQ enable is set to 1,

the pen interrupt request output is disabled.

The pen interrupt equivalent output circuitry is outlined in

Figure 35. This is a digital logic output with an internal 50 kΩ

pull-up resistor, which means it does not need an external pull-

up. The PENIRQ output idles high, and the PENIRQ circuitry

is always enabled in master mode (ADC mode = 11), except

during conversions.

X+

TOUCH

SCREEN

Y+

50k

Ω

Y–

X–

PENIRQ

ENABLE

PENIRQ

VCC

Figure 35. PENIRQ Output Equivalent Circuit

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