APPLICATIONS INFORMATION

Theory of Operation

Input Configuration

1000 W

1000 W

10 W

10 W

VCM

3 pF

3pF

AGND

S0293-02

INP

INM

AVDD5

AVDD5

ADS548x

AGND

AGND

~ 2 nH Bond Wire

~ 2 nH Bond Wire

~ 200fF

Package

~ 200fF

Package

~ 200fF

BondPad

~ 200fF

BondPad

Analog

Inputs

Bipolar

Transistor

Buffer

Bipolar

Transistor

Buffer

TrackandHold,

1

Stage

st

Pipeline

ADS5481

ADS5482

ADS5483

The ADS5481/ADS5482/ADS5483 (ADS548x) is a 16-bit, 80-135MSPS family of monolithic pipeline ADCs. The

bipolar analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide

LVDS-compatible outputs. Prior to the track-and-hold, the analog input signal passes through a high-performance

bipolar buffer. The buffer presents a high and consistent impedance to the analog inputs. The buffer isolates the

board circuitry external to the ADC from the sampling glitches caused by the track-and-hold in the ADC. The

conversion process is initiated by the falling edge of the external input clock. At that instant, the differential input

signal is captured by the input track-and-hold, and the input sample is converted sequentially by a series of lower

resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling

clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in

a data latency of 4.5 clock cycles, after which the output data are available as a 16-bit parallel word, coded in

offset binary format.

The analog input for the ADS548x consists of an analog pseudo-differential buffer followed by a bipolar transistor

T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and presents

a high impedance that is easy to drive at high input frequencies, compared to an ADC without a buffered input.

The input common-mode is set internally through a 1000-

Ω resistor connected from 3.1 V to each of the inputs.

This configuration results in a differential input impedance of 2 k

Ω at 0 Hz.

Figure 60. Analog Input Circuit

For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings

symmetrically between (3.1 V + 0.75 V) and (3.1 V – 0.75 V). This range means that each input has a maximum

the characteristics of performance versus input amplitude demonstrated in Figure 6 through Figure 10. For

signal will also likely help any components in the signal chain prior to the ADC to be more linear and provide

better distortion.

Copyright © 2008, Texas Instruments Incorporated

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