SNR(dBc)= 20

LOG10(2

f

j

)

-

p ´

´

´

´

IN

TOTAL

(1)

j

=(j

+j

)

TOTAL

ADC

CLOCK

2

1/2

2

(2)

CLKP

CLKM

REF

400 MHz (To Transmit DAC)

100 MHz (To DSP)

100 MHz (To FPGA)

To Other

10 MHz

400MHz

100 MHz

Low Jitter Oscillator

BPF

LVCMOS

XFMR

AMP

AMP and/or BPF Optional

BoardMaster

ReferenceClock

(Highor LowJitter)

VCO/

VCXO

CDC

(ClockDistributionChip)

Ex: TI CDCE72010

LVPECL

or

LVCMOS

ADC

TI ADS548x

B0268-01

ADS5481

ADS5482

ADS5483

Equation 1 and Equation 2 are used to estimate the required clock source jitter.

where:

Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the

clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.

For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not

required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see

Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC

Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI

required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too

low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed

between the CDC and the BPF, as its harmonics and wide-band noise will be reduced by the BPF.

Figure 75 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCE72010

with the clock signal path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult

to estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost

amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter

provided by the CDC is still not adequate. The total jitter at the CDCE72010 output depends largely on the phase

noise of the VCXO/VCO selected, as well as from the CDCE72010 itself.

Consult the CDCE72010 data sheet for proper schematic and specifications regarding allowable input and output

frequency and amplitude ranges.

Figure 75. Optimum Jitter Clock Circuit

Copyright © 2008, Texas Instruments Incorporated

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