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ISP1505CBS Datasheet(PDF) 16 Page - NXP Semiconductors |
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ISP1505CBS Datasheet(HTML) 16 Page - NXP Semiconductors |
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16 / 76 page  ISP1505A_ISP1505C_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 26 August 2008 15 of 75 NXP Semiconductors ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1505 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0] bus definition changes to that shown in Table 5. To enter 6-pin serial mode, the link sets the 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial mode, the link asserts STP. This is provided primarily for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM register bit must be set to logic 1. For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. 8.1.4 3-pin full-speed or low-speed serial mode If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1505 to 3-pin serial mode. In 3-pin serial mode, the data bus definition changes to that shown in Table 6. To enter 3-pin serial mode, the link sets the 3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial mode, the link asserts STP. This is primarily provided for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM register bit must be set to logic 1. For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. Reserved DATA2 O reserved; the ISP1505 will drive this pin to LOW INT DATA3 O active HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs Reserved DATA[7:4] O reserved; the ISP1505 will drive these pins to LOW Table 4. Signal mapping during low-power mode …continued Signal Maps to Direction Description Table 5. Signal mapping for 6-pin serial mode Signal Maps to Direction Description TX_ENABLE DATA0 I active HIGH transmit enable TX_DAT DATA1 I transmit differential data on DP and DM TX_SE0 DATA2 I transmit single-ended zero on DP and DM INT DATA3 O active HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs RX_DP DATA4 O single-ended receive data from DP RX_DM DATA5 O single-ended receive data from DM RX_RCV DATA6 O differential receive data from DP and DM Reserved DATA7 O reserved; the ISP1505 will drive this pin to LOW |
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