ISP1505CBS datasheet(33/76 Pages) NXP

33 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

32 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

9.9 Preamble

Preamble packets are headers to low-speed packets that must travel over a full-speed

bus, between a host and a hub. To enter preamble mode, the link sets

XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the

ISP1505 operates just as in full-speed mode, and sends all data with the full-speed rise

time and fall time. Whenever the link transmits a USB packet in preamble mode, the

ISP1505 will automatically send a preamble header at full-speed bit rate before sending

the link packet at low-speed bit rate. The ISP1505 will ensure a minimum gap of four

full-speed bit times between the last bit of the full-speed PRE PID and the ﬁrst bit of the

low-speed packet SYNC. The ISP1505 will drive a J for at least one full-speed bit time

after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus.

An example transmit packet is shown in Figure 13.

In preamble mode, the ISP1505 can also receive low-speed packets from the full-speed

bus.

Fig 12. High-speed receive-to-transmit packet timing

004aaa713

DP or

DATA

EOP

IDLE

SYNC

CLOCK

DN−4

DN−3

DATA

[7:0]

TXCMD

DIR

STP

NXT

RX end delay

(three to eight clocks)

link decision time (1 to 14 clocks)

TX start delay

(one to two clocks)

USB interpacket delay (8 to 192 high-speed bit times)

DN−2

DN−1

turnaround

ISP1505CBS Datasheet(PDF) 33 Page - NXP Semiconductors

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