ISP1505CBS datasheet(62/76 Pages) NXP

62 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

61 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

15.1 ULPI timing

ULPI interface timing requirements are given in Figure 25. This timing applies to

synchronous mode only. All timing is measured with respect to the ISP1505 CLOCK pin.

All signals are clocked on the rising edge of CLOCK.

Fig 21. Rise time and fall time

Fig 22. Timing of TX_DAT and TX_SE0 to DP and DM

Fig 23. Timing of TX_ENABLE to DP and DM

Fig 24. Timing of DP and DM to RX_RCV, RX_DP and

RX_DM

004aaa861

VOL

tHSR, tFR, tLR

tHSF, tFF, tLF

VOH

90 %

10 %

90 %

004aaa573

VOL

VOH

tPHL(drv)

tPLH(drv)

VCRS

0.9 V

1.8 V

0 V

logic input

differential

data lines

004aaa574

VOL

VOH

tPZH

tPZL

tPHZ

tPLZ

VOH − 0.3 V

VOL + 0.3 V

VCRS

0.9 V

1.8 V

0 V

logic

input

differential

data lines

tPLH(se)

tPHL(se)

004aaa575

VOL

VOH

tPHL(rcv)

tPLH(rcv)

VCRS

0.9 V

2.0 V

0.8 V

logic output

differential

data lines

Fig 25. ULPI interface timing

CLOCK

CONTROL IN

(STP)

DATA IN

(8-BIT)

tsu(STP) th(STP)

tsu(DATA) th(DATA)

CONTROL OUT

(DIR, NXT)

DATA OUT

(8-BIT)

004aaa722

td(DIR),

td(NXT)

td(DATA)

td(DIR),

td(NXT)

ISP1505CBS Datasheet(PDF) 62 Page - NXP Semiconductors

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