ISP1505CBS datasheet(73/76 Pages) NXP

73 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

72 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

24. Tables

Table 1.

Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3.

ULPI signal description . . . . . . . . . . . . . . . . . .13

Table 4.

Signal mapping during low-power mode . . . . .14

Table 5.

Signal mapping for 6-pin serial mode . . . . . . .15

Table 6.

Signal mapping for 3-pin serial mode . . . . . . .16

Table 7.

Operating states and their corresponding

resistor settings . . . . . . . . . . . . . . . . . . . . . . . .16

Table 8.

TXCMD byte format . . . . . . . . . . . . . . . . . . . . .22

Table 9.

RXCMD byte format . . . . . . . . . . . . . . . . . . . . .23

Table 10. LINESTATE[1:0] encoding for upstream

facing ports: peripheral . . . . . . . . . . . . . . . . . .23

Table 11. LINESTATE[1:0] encoding for downstream

facing ports: host . . . . . . . . . . . . . . . . . . . . . . .24

Table 12. Encoded VBUS voltage state . . . . . . . . . . . . . .24

Table 13. VBUS indicators in RXCMD required for

typical applications . . . . . . . . . . . . . . . . . . . . . .25

Table 14. Encoded USB event signals . . . . . . . . . . . . . .26

Table 15. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .30

Table 16. Link decision times . . . . . . . . . . . . . . . . . . . . .31

Table 17. Immediate register set overview . . . . . . . . . . .43

Table 18. Extended register set overview . . . . . . . . . . . .43

Table 19. Vendor ID Low register (address R = 00h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 20. Vendor ID High register (address R = 01h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 21. Product ID Low register (address R = 02h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 22. Product ID High register (address R = 03h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 23. Function Control register (address R =

04h to 06h, W = 04h, S = 05h, C = 06h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 24. Function Control register (address R =

04h to 06h, W = 04h, S = 05h, C = 06h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 25. Interface Control register (address R =

07h to 09h, W = 07h, S = 08h, C = 09h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 26. Interface Control register (address R =

07h to 09h, W = 07h, S = 08h, C = 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 27. OTG Control register

(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,

C = 0Ch) bit allocation . . . . . . . . . . . . . . . . . . .46

Table 28. OTG Control register

(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,

C = 0Ch) bit description . . . . . . . . . . . . . . . . . .47

Table 29. USB Interrupt Enable Rising Edge register

(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,

C = 0Fh) bit allocation . . . . . . . . . . . . . . . . . . .47

Table 30. USB Interrupt Enable Rising Edge register

(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,

C = 0Fh) bit description . . . . . . . . . . . . . . . . . .48

Table 31. USB Interrupt Enable Falling Edge register

(address R = 10h to 12h, W = 10h, S = 11h,

C = 12h) bit allocation . . . . . . . . . . . . . . . . . . . 48

Table 32. USB Interrupt Enable Falling Edge register

(address R = 10h to 12h, W = 10h, S = 11h,

C = 12h) bit description . . . . . . . . . . . . . . . . . . 48

Table 33. USB Interrupt Status register

(address R = 13h) bit allocation . . . . . . . . . . . 48

Table 34. USB Interrupt Status register

(address R = 13h) bit description . . . . . . . . . . 49

Table 35. USB Interrupt Latch register

(address R = 14h) bit allocation . . . . . . . . . . . 49

Table 36. USB Interrupt Latch register

(address R = 14h) bit description . . . . . . . . . . 49

Table 37. Debug register (address R = 15h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 38. Debug register (address R = 15h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 39. Scratch register (address R = 16h to 18h,

W = 16h, S = 17h, C = 18h) bit description . . . 50

Table 40. Power Control register

(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,

C = 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 50

Table 41. Power Control register

(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,

C = 3Fh) bit description . . . . . . . . . . . . . . . . . . 51

Table 42. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 43. Recommended operating conditions . . . . . . . . 53

Table 44. Static characteristics: supply pins . . . . . . . . . . 54

Table 45. Static characteristics: digital pins

(CLOCK, DIR, STP, NXT, DATA[7:0],

RESET_N/PSW_N) . . . . . . . . . . . . . . . . . . . . . 54

Table 46. Static characteristics: pin VBUS/FAULT . . . . . . 55

Table 47. Static characteristics: analog I/O pins

(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 48. Static characteristics: VBUS comparators . . . . 57

Table 49. Static characteristics: VBUS resistors . . . . . . . . 57

Table 50. Static characteristics: resistor reference . . . . . 57

Table 51. Dynamic characteristics: reset and clock . . . . 58

Table 52. Dynamic characteristics: digital I/O pins . . . . . 58

Table 53. Dynamic characteristics: analog I/O pins

(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 54. Recommended bill of materials . . . . . . . . . . . . 62

Table 55. SnPb eutectic process (from J-STD-020C) . . . 67

Table 56. Lead-free process (from J-STD-020C) . . . . . . 67

Table 57. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 58. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 70

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