ISP1505CBS datasheet(71/76 Pages) NXP

71 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

70 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

21. Revision history

Table 58.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

ISP1505A_ISP1505C_3

20080826

Product data sheet

ISP1505A_ISP1505C_2

Modiﬁcations:

• Changed On-The-Go Supplement to the USB 2.0 Speciﬁcation from Rev. 1.2 to Rev. 1.3.

• Section 2 “Features”: updated.

• Section 8.2 “USB and OTG state transitions”: updated the ﬁrst sentence.

• Section “OTG devices”: updated the last sentence.

• Section 9.10.1 “Full-speed and low-speed host-initiated suspend and resume”: updated the

second list item.

• Section 9.10.2 “High-speed suspend and resume”: updated the second list item.

• Table 41 “Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit

description”: updated description for bits 3 and 2.

• Removed reference to input clock mode from the following sections:

– Section 2 “Features”

– Section 5 “Block diagram”

– Table 2 “Pin description”

– Section 7.5 “Crystal oscillator and PLL”

– Section 7.10.2 “VCC(I/O)”

– Section 7.10.8 “XTAL1 and XTAL2”

– Section 7.10.13 “CLOCK”

– Table 3 “ULPI signal description”

– Section 9.3 “Power-up, reset and bus idle sequence”

– Table 42 “Limiting values”

– Table 43 “Recommended operating conditions”

– Table 45 “Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0],

RESET_N/PSW_N)”

– Table 51 “Dynamic characteristics: reset and clock”

– Table 52 “Dynamic characteristics: digital I/O pins”

– Section 16 “Application information”

ISP1505A_ISP1505C_2

20070913

Product data sheet

ISP1505A_ISP1505C_1

Modiﬁcations:

• Section 9.4.2 “Fault detection”: updated.

• Section “Standard USB host controllers”: updated the ﬁrst list item.

• Section 10.2 “Extended register set”: updated the second paragraph.

• Table 42 “Limiting values”: added VI on the DP and DM pins, and added Table note 1.

• Table 51 “Dynamic characteristics: reset and clock”: added

δi(XTAL1) and Table note 1.

• Table 52 “Dynamic characteristics: digital I/O pins”: updated.

• Section 16 “Application information”: updated.

ISP1505A_ISP1505C_1

20061019

Product data sheet

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