ISP1505CBS datasheet(21/76 Pages) NXP

21 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

20 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

9.3.1 Interface protection

By default, the ISP1505 enables a weak pull-up resistor on STP. If the STP pin is

unexpectedly HIGH at any time, the ISP1505 will protect the ULPI interface by enabling

weak pull-down resistors on DATA[7:0].

The interface protect feature prevents unwanted activity of the ISP1505 whenever the

ULPI interface is not correctly driven by the link. For example, when the link powers up

more slowly than the ISP1505.

t1 = VCC and VCC(I/O) are applied to the ISP1505. The ISP1505 regulator starts to turn on.

t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive

either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during tPWRUP.

t3 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a deﬁned level.

DIR is driven to HIGH and the other pins are driven to LOW.

t4 = The internal PLL is stabilized after tstartup(PLL). If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will

be stabilized after tstartup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW.

The DIR pin will remain LOW before the link issues a RESET command to the ISP1505.

t5 = The power-up sequence is completed and the ULPI bus interface is ready for use.

Fig 4.

Power-up and reset sequence required before the ULPI bus is ready for use

CLOCK

TXCMD

DIR

DATA[7:0]

STP

NXT

004aaa885

RESET command

internal clocks stable

internal reset

RXCMD

update

bus idle

VCC

VCC(I/O)

REG1V8

internal

REG1V8

detector

internal

POR

XTAL1

tstartup(PLL)

tPWRUP

ISP1505CBS Datasheet(PDF) 21 Page - NXP Semiconductors

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