ISP1505CBS datasheet(74/76 Pages) NXP

74 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

73 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

25. Figures

Fig 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2.

Pin conﬁguration HVQFN24; top view . . . . . . . . . .5

Fig 3.

Internal power-on reset timing . . . . . . . . . . . . . . .18

Fig 4.

Power-up and reset sequence required

before the ULPI bus is ready for use . . . . . . . . . .20

Fig 5.

Interface behavior with respect to RESET_N. . . .21

Fig 6.

Single and back-to-back RXCMDs from the

ISP1505 to the link. . . . . . . . . . . . . . . . . . . . . . . .23

Fig 7.

RXCMD A_VBUS_VLD indicator source . . . . . . .25

Fig 8.

Example of register write, register read,

extended register write and extended

Fig 9.

USB reset and high-speed detection

handshake (chirp) sequence . . . . . . . . . . . . . . . .29

Fig 10. Example of using the ISP1505 to transmit and

receive USB data . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 11. High-speed transmit-to-transmit packet timing. . .31

Fig 12. High-speed receive-to-transmit packet timing . . .32

Fig 13. Preamble sequence . . . . . . . . . . . . . . . . . . . . . . .33

Fig 14. Full-speed suspend and resume . . . . . . . . . . . . .34

Fig 15. High-speed suspend and resume . . . . . . . . . . . .36

Fig 16. Remote wake-up from low-power mode . . . . . . .38

Fig 17. Transmitting USB packets without

the automatic SYNC and EOP generation. . . . . .39

Fig 18. Example of transmit followed by receive in

6-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 19. Example of transmit followed by receive in

3-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 20. Human body ESD test model. . . . . . . . . . . . . . . .52

Fig 21. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .61

Fig 22. Timing of TX_DAT and TX_SE0 to DP and DM . .61

Fig 23. Timing of TX_ENABLE to DP and DM. . . . . . . . .61

Fig 24. Timing of DP and DM to RX_RCV, RX_DP

and RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Fig 25. ULPI interface timing . . . . . . . . . . . . . . . . . . . . . .61

Fig 26. Using the ISP1505 with a USB host controller;

external 5 V source with built-in FAULT and

external crystal. . . . . . . . . . . . . . . . . . . . . . . . . . .63

Fig 27. Using the ISP1505 with a peripheral controller;

external square wave input on pin XTAL1 . . . . . .64

Fig 28. Package outline SOT616-3 (HVQFN24) . . . . . . .65

Fig 29. Temperature proﬁles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

ISP1505CBS Datasheet(PDF) 74 Page - NXP Semiconductors

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