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ISP1505CBS Datasheet(PDF) 34 Page - NXP Semiconductors |
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ISP1505CBS Datasheet(HTML) 34 Page - NXP Semiconductors |
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34 / 76 page ![]() ISP1505A_ISP1505C_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 26 August 2008 33 of 75 NXP Semiconductors ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 9.10 USB suspend and resume 9.10.1 Full-speed and low-speed host-initiated suspend and resume Figure 14 illustrates how a host or a hub places a full-speed or low-speed peripheral into suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note that Figure 14 timing is not to scale, and does not show all RXCMD LINESTATE updates. The sequence of events for a host and a peripheral, both with ISP1505, is as follows: 1. Idle: Initially, the host and the peripheral are idle. The host has its 15 k Ω pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 Ω terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 k Ω pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is set to 1b). 2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state. The peripheral link places the PHY into low-power mode by clearing the SUSPENDM bit in the Function Control register, causing the PHY to draw only suspend current. The host may or may not be powered down. 3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to 10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on LINESTATE, and asserts STP to wake up the PHY. 4. EOP: When STP is asserted, the ISP1505 on the host side automatically appends an EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1505 on the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0] to 00b for normal operation. The peripheral link sees the EOP and also resumes normal operation. DP and DM timing is not to scale. Fig 13. Preamble sequence CLOCK D0 TXCMD (low-speed packet ID) D1 DATA[7:0] DIR STP NXT 004aaa714 DP or DM FS SYNC FS PRE ID IDLE (min 4 FS bits) LS SYNC LS PID LS D0 LS D1 |
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