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ISP1505CBS Datasheet(PDF) 49 Page - NXP Semiconductors |
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ISP1505CBS Datasheet(HTML) 49 Page - NXP Semiconductors |
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49 / 76 page  ISP1505A_ISP1505C_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 26 August 2008 48 of 75 NXP Semiconductors ISP1505A; ISP1505C ULPI HS USB host and peripheral transceiver 10.1.6 USB Interrupt Enable Falling Edge register The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB Interrupt Status register change from logic 1 to logic 0. By default, all transitions are enabled. See Table 31. 10.1.7 USB Interrupt Status register This register (see Table 33) indicates the current value of the interrupt source signal. Table 30. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit description Bit Symbol Description 7 to 4 - reserved 3 SESS_END_R Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on SESS_END. 2 SESS_VALID_R Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on SESS_VLD. 1 VBUS_VALID_R VBUS Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on A_VBUS_VLD. 0 HOST_DISCON_R Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on HOST_DISCON. Table 31. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol reserved SESS_ END_F SESS_ VALID_F VBUS_ VALID_F HOST_ DISCON_F Reset 00011111 Access R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C Table 32. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit description Bit Symbol Description 7 to 4 - reserved 3 SESS_END_F Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on SESS_END. 2 SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on SESS_VLD. 1 VBUS_VALID_F VBUS Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on A_VBUS_VLD. 0 HOST_DISCON_F Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on HOST_DISCON. Table 33. USB Interrupt Status register (address R = 13h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol reserved SESS_ END SESS_ VALID VBUS_ VALID HOST_ DISCON Reset X X X 00000 Access RRRRRRRR |
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