ISP1505CBS datasheet(29/76 Pages) NXP

29 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

28 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

than 7 ms after reset time T0. If the peripheral is in low-power mode, it must wake

up its clock within 5.6 ms, leaving 200

µs for the link to start transmitting the

Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).

b. Host chirp: If the host does not detect the peripheral chirp, it must continue

asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for

no less than 2.5

µs, then no more than 100 µs after the bus leaves the Chirp K

state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks

and Js. Each Chirp K or Chirp J must last for no less than 40

µs and no longer than

µs.

c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each

Chirp K and Chirp J must be detected for at least 2.5

µs. After seeing that

minimum sequence, the peripheral sets TERMSELECT = 0b and

OPMODE[1:0] = 00b. The peripheral is now in high-speed mode and sees !squelch

(01b on LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it

knows that the host has completed chirp and waits for Hi-Speed USB trafﬁc to

begin. After transmitting the chirp sequence, the host changes OPMODE[1:0] to

00b and begins sending USB packets.

For more information, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

ISP1505CBS Datasheet(PDF) 29 Page - NXP Semiconductors