ISP1505CBS datasheet(52/76 Pages) NXP

52 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

51 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

10.2 Extended register set

Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This

means a read, write, set or clear operation to these extended addresses will operate on

the immediate register set.

Addresses 40h to FFh are not implemented. Operating on these addresses may result in

undeﬁned behavior of the PHY.

Table 41.

Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description

Bit

Symbol

Description

7 to 4

reserved; the link must never write logic 1 to these bits.

BVALID_FALL

BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID

changes from HIGH to LOW, the ISP1505 will send an RXCMD to the link with the ALT_INT

bit set to logic 1.

This bit is optional and is not necessary for OTG devices. This bit is provided for debugging

purposes. The session valid comparator should be used instead.

BVALID_RISE

BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID

changes from LOW to HIGH, the ISP1505 will send an RXCMD to the link with the ALT_INT

bit set to logic 1.

This bit is optional and is not necessary for OTG devices. This bit is provided for debugging

purposes. The session valid comparator should be used instead.

reserved

IGNORE_RESET

Ignore Reset: Selects between the RESET_N and PSW_N functions of the

RESET_N/PSW_N pin. The link must set this bit to logic 1, if PSW_N is used in a ganged

mode conﬁguration.

0b — The RESET_N/PSW_N pin behaves as an active-LOW reset input (RESET_N). This is

the default setting.

1b — The RESET_N/PSW_N pin behaves as an active-LOW power switch output (PSW_N).

ISP1505CBS Datasheet(PDF) 52 Page - NXP Semiconductors