ISP1505CBS datasheet(13/76 Pages) NXP

13 / 76 page

ISP1505A_ISP1505C_3

Product data sheet

Rev. 03 — 26 August 2008

12 of 75

NXP Semiconductors

ISP1505A; ISP1505C

ULPI HS USB host and peripheral transceiver

7.10.10 DIR

ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1505

holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1505

listens for data from the link. The ISP1505 pulls DIR to HIGH only when it has data to

send to the link, which is for one of two reasons:

• To send the USB receive data, RXCMD status updates and register reads data to the

link.

• To block the link from driving the data bus during power-up, reset and low-power

mode (suspend).

For details on DIR usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

7.10.11 STP

ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet

or a register write operation. When DIR is asserted, the link can optionally assert STP to

abort the ISP1505, causing it to deassert DIR in the next clock cycle. A weak pull-up

resistor is incorporated into the STP pin as part of the interface protect feature. For details,

see Section 9.3.1.

For details on STP usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

7.10.12 NXT

ULPI next data output pin. The ISP1505 holds NXT at LOW, by default. When DIR is LOW

and the link is sending data to the ISP1505, NXT will be asserted to notify the link to

provide the next data byte. When DIR is at HIGH and the ISP1505 is sending data to the

link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not

used for the register read data or the RXCMD status update.

For details on NXT usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

7.10.13 CLOCK

A 60 MHz interface clock to synchronize the ULPI bus. The ISP1505 provides two

clocking options:

• A crystal is attached between the XTAL1 and XTAL2 pins.

• A clock is driven into the XTAL1 pin, with the XTAL2 pin left ﬂoating.

For details on CLOCK usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1.

7.10.14 GND (die pad)

Global ground signal. The die pad is exposed on the underside of the package as a

ground plate. This acts as a ground to all circuits in the ISP1505. To ensure correct

operation of the ISP1505, GND must be soldered to the cleanest ground available.

ISP1505CBS Datasheet(PDF) 13 Page - NXP Semiconductors

ISP1505CBS Datasheet(HTML) 13 Page - NXP Semiconductors

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