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PCI1221 Datasheet(PDF) 118 Page - Texas Instruments |
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PCI1221 Datasheet(HTML) 118 Page - Texas Instruments |
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118 / 123 page  118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 62. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles WAIT-STATE BITS TS1 – 0 = 01 (PCLK/ns) I/O 2/60 Memory WS1 0 2/60 Memory WS1 1 3/90 timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see Note 6 and Figure 28) ALTERNATE SYMBOL MIN MAX UNIT tsu Setup time, CE1 and CE2 before WE/OE low T1 60 ns tsu Setup time, CA25–CA0 before WE/OE low T2 tsu(A)+2PCLK ns tsu Setup time, REG before WE/OE low T3 90 ns tpd Propagation delay time, WE/OE low to WAIT low T4 ns tw Pulse duration (width), WE/OE low T5 200 ns th Hold time, WE/OE low after WAIT high T6 ns th Hold time, CE1 and CE2 after WE/OE high T7 120 ns tsu Setup time (read), CDATA15–CDATA0 valid before OE high T8 ns th Hold time (read), CDATA15–CDATA0 valid after OE high T9 0 ns th Hold time, CA25–CA0 and REG after WE/OE high T10 th(A)+1PCLK ns tsu Setup time (write), CDATA15–CDATA0 valid before WE low T11 60 ns th Hold time (write), CDATA15–CDATA0 valid after WE low T12 240 ns NOTE 6: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock. timing requirements over recommended ranges of supply voltage and operating free-air temperature, I/O cycles (see Figure 29) ALTERNATE SYMBOL MIN MAX UNIT tsu Setup time, REG before IORD/IOWR low T13 60 ns tsu Setup time, CE1 and CE2 before IORD/IOWR low T14 60 ns tsu Setup time, CA25–CA0 valid before IORD/IOWR low T15 tsu(A)+2PCLK ns tpd Propagation delay time, IOIS16 low after CA25–CA0 valid T16 35 ns tpd Propagation delay time, IORD low to WAIT low T17 35 ns tw Pulse duration (width), IORD/IOWR low T18 TcA ns th Hold time, IORD low after WAIT high T19 ns th Hold time, REG low after IORD high T20 0 ns th Hold time, CE1 and CE2 after IORD/IOWR high T21 120 ns th Hold time, CA25–CA0 after IORD/IOWR high T22 th(A)+1PCLK ns tsu Setup time (read), CDATA15–CDATA0 valid before IORD high T23 10 ns th Hold time (read), CDATA15–CDATA0 valid after IORD high T24 0 ns tsu Setup time (write), CDATA15–CDATA0 valid before IOWR low T25 90 ns th Hold time (write), CDATA15–CDATA0 valid after IOWR high T26 90 ns |
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