PCI1221 datasheet(114/123 Pages) TI

114 / 123 page

114

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PCI clock/reset timing requirements over recommended ranges of supply voltage and operating

free-air temperature (see Figure 25 and Figure 26)

PARAMETER

ALTERNATE

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

Cycle time, PCLK

tcyc

twH

Pulse duration (width), PCLK high

thigh

twL

Pulse duration (width), PCLK low

tlow

∆v/∆t

Slew rate, PCLK

tr, tf

V/ns

Pulse duration (width), RSTIN

trst

tsu

Setup time, PCLK active at end of RSTIN

trst-clk

100

PCI timing requirements over recommended ranges of supply voltage and operating free-air

temperature (see Note 4 and Figure 24 and Figure 27)

PARAMETER

ALTERNATE

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

t d

Propagation delay time,

PCLK-to-shared signal

valid delay time

tval

CL = 50 pF,

tpd

See Note 5

PCLK-to-shared signal

invalid delay time

tinv

See Note 5

ten

Enable time, high impedance-to-active delay time from PCLK

ton

tdis

Disable time, active-to-high impedance delay time from PCLK

toff

tsu

Setup time before PCLK valid

tsu

Hold time after PCLK high

NOTES:

4. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type

of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time,

and th = hold time.

5. PCI shared signals are AD31–0, C/BE3–0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.

PCI1221 Datasheet(PDF) 114 Page - Texas Instruments

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