PCI1221 datasheet(110/123 Pages) TI

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socket power management register

Bit

Name

Socket power management

Type

R/W

Default

Bit

Name

Socket power management

Type

R/W

Default

Socket power management

Type:

Read only, read/write (see individual bit descriptions)

Offset:

CardBus socket address + 20h

Default:

0000 0000h

Description: This register provides power management control over the socket through a mechanism for

slowing or stopping the clock on the card interface when the card is idle. See Table 58 for a

complete description of the register contents.

Table 58. Socket Power Management Register

BIT

SIGNAL

TYPE

FUNCTION

31-26

RSVD

Reserved. Bits 31-26 are read only and return 0s when read.

SKTACCES

Socket access status. This bit provides information on when a socket access has occurred. This bit is

cleared by a read access.

0 = A PC card access has not occurred (default).

1 = A PC card access has occurred.

SKTMODE

Socket mode status. This bit provides clock mode information.

0 = Clock is operating normally.

1 = Clock frequency has changed.

23-17

RSVD

Reserved. Bits 23-17 are read only and return 0s when read.

CLKCTRLEN

R/W

CardBus clock control enable. When bit 16 is set, clock control (CLKCTRL bit 0) is enabled.

0 = Clock control is disabled (default).

1 = Clock control is enabled.

15-1

RSVD

Reserved. Bits 15-1 are read only and return 0s when read.

CLKCTRL

R/W

CardBus clock control. This bit determines whether the CB CLKRUN protocol will attempt to stop or slow

the CB clock during idle states. Bit 16 enables this bit.

0 = Allows CB CLKRUN protocol to stop the CB clock (default).

1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16.

PCI1221 Datasheet(PDF) 110 Page - Texas Instruments

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