PCI1221 datasheet(107/123 Pages) TI

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Table 55. Socket Present-State Register

BIT

SIGNAL

TYPE

FUNCTION

YVSOCKET

YV socket. Bit 31 indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The PCI1221

does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event

XVSOCKET

XV socket. Bit 30 indicates whether or not the socket can supply VCC = X.X V to PC Cards. The PCI1221

does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force

event register. This bit is hardwired to 0.

3VSOCKET

3-V socket. Bit 29 indicates whether or not the socket can supply VCC = 3.3 V to PC Cards. The PCI1221

does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force event

5VSOCKET

5-V socket. Bit 28 indicates whether or not the socket can supply VCC = 5 V to PC Cards. The PCI1221

does support 5-V VCC; therefore, this bit is always set unless overridden by the socket force event

27-14

RSVD

Reserved. Bits 27-14 are read only and return 0s when read.

YVCARD

YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V.

XVCARD

XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V.

3VCARD

3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V.

5VCARD

5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V.

BADVCCREQ

Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an

invalid voltage.

0 = Normal operation (default)

1 = Invalid VCC request by host software

DATALOST

Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle

did not terminate properly or because write data still resides in the PCI1221.

0 = Normal operation (default)

1 = Potential data loss due to card removal

NOTACARD

Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is

not updated until a valid PC Card is inserted into the socket.

0 = Normal operation (default)

1 = Unrecognizable PC Card detected

IREQCINT

READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card

interface.

0 = READY(IREQ)//CINT low

1 = READY(IREQ)//CINT high

CBCARD

CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not

updated until another card interrogation sequence occurs (card insertion).

16BITCARD

16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated

until another card interrogation sequence occurs (card insertion).

PWRCYCLE

Power cycle. Bit 3 indicates that the status of each card powering request. This bit is encoded as:

0 = Socket powered down (default)

1 = Socket powered up

CDETECT2

CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during

card interrogation are not reflected here.

0 = CCD2 low (PC Card may be present)

1 = CCD2 high (PC Card not present)

CDETECT1

CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during

card interrogation are not reflected here.

0 = CCD1 low (PC Card may be present)

1 = CCD1 high (PC Card not present)

CARDSTS

CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface.

0 = CSTSCHG low

1 = CSTSCHG high

PCI1221 Datasheet(PDF) 107 Page - Texas Instruments

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