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PCI1221 Datasheet(PDF) 103 Page - Texas Instruments |
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PCI1221 Datasheet(HTML) 103 Page - Texas Instruments |
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103 / 123 page  103 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA memory window 0–4 page register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 0–4 page Type: Read/write Offset: CardBus socket address + 840h 841h, 842h, 843h, 844h Default: 00h Description: The upper eight bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256 16M-byte regions in the 4G-byte PCI address space. These registers are only accessible when the ExCA registers are memory mapped, i.e., these registers can not be accessed using the index/data I/O scheme. CardBus socket registers (functions 0 and 1) The PCMCIA CardBus specification requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI1221 provides the CardBus socket/ExCA base address register (PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each socket has a separate base address register for accessing the CardBus socket registers (see Figure 23). Table 52 gives the location of the socket registers in relation to the CardBus socket/ExCA base address. The PCI1221 implements an additional register at offset 20h that provides power management control for the socket. CardBus Socket/ExCA Base Address 16-Bit Legacy-Mode Base Address 10h 44h NOTE: The CardBus socket/ExCA base address mode register is separate for functions 0 and 1. PCI1221 Configuration Registers CardBus Socket A Registers Host Memory Space 00h ExCA Registers Card A 20h 800h 844h Offset CardBus Socket B Registers Host Memory Space 00h ExCA Registers Card B 20h 800h 844h Offset Offset Figure 23. Accessing CardBus Socket Registers Through PCI Memory |
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