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PCI1221 Datasheet(PDF) 104 Page - Texas Instruments |
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PCI1221 Datasheet(HTML) 104 Page - Texas Instruments |
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104 / 123 page  104 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 52. CardBus Socket Registers REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket Power Management 20h socket event register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket event Type R R R R R R R R R R R R R/C R/C R/C R/C Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Socket event Type: Read only, read/write, read/clear (see individual bit descriptions) Offset: CardBus socket address + 00h Default: 0000 0000h Description: The socket event register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software must clear this register before enabling interrupts. If it is not cleared, when interrupts are enabled an interrupt is generated (but not masked) based on any bit set. See Table 53 for a complete description of the register contents. Table 53. Socket Event Register BIT SIGNAL TYPE FUNCTION 31-4 RSVD R Reserved. Bits 31-4 are read only and return 0s when read. 3 PWREVENT R/C Power cycle. Bit 3 is set when the PCI1221 detects that the PWRCYCLE bit in the socket present-state register has changed. This bit is cleared by writing a 1. 2 CD2EVENT R/C CCD2. Bit 2 is set when the PCI1221 detects that the CDETECT2 field in the socket present-state register has changed. This bit is cleared by writing a 1. 1 CD1EVENT R/C CCD1. Bit 3 is set when the PCI1221 detects that the CDETECT1 field in the socket present-state register has changed. This bit is cleared by writing a 1. 0 CSTSEVENT R/C CSTSCHG. Bit 0 is set when the CARDSTS field in the socket present-state register has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For 16-bit PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1. |
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