PCI1221 datasheet(105/123 Pages) TI

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socket mask register

Bit

Name

Socket mask

Type

Default

Bit

Name

Socket mask

Type

R/W

Default

Socket mask

Type:

Read only, read/write (see individual bit descriptions)

Offset:

CardBus socket address + 04h

Default:

0000 0000h

Description: The socket mask register allows software to control the CardBus card events that generate a

status change interrupt. The state of these mask bits does not prevent the corresponding bits

from reacting in the socket event register. See Table 54 for a complete description of the

Table 54. Socket Mask Register

BIT

SIGNAL

TYPE

FUNCTION

31-4

RSVD

Reserved. Bits 31-4 are read only and return 0s when read.

PWRMASK

R/W

Power cycle. Bit 3 masks the PWRCYCLE bit in the socket present state register from causing a status

change interrupt.

0 = PWRCYCLE event does not cause CSC interrupt (default).

1 = PWRCYCLE event causes CSC interrupt.

2-1

CDMASK

R/W

Card detect mask. Bits 2-1 mask the CDETECT1 and CDETECT2 bits in the socket present-state register

from causing a CSC interrupt.

00 = Insertion/removal does not cause CSC interrupt (default).

01 = Reserved (undefined)

10 = Reserved (undefined)

11 = Insertion/removal causes CSC interrupt.

CSTSMASK

R/W

CSTSCHG mask. Bit 0 masks the CARDSTS field in the socket present-state register from causing a CSC

interrupt.

0 = CARDSTS event does not cause CSC interrupt (default).

1 = CARDSTS event causes CSC interrupt.

PCI1221 Datasheet(PDF) 105 Page - Texas Instruments

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