UCC29421, UCC29422, UCC39421, UCC39422

MULTIMODE HIGHFREQUENCY PWM CONTROLLER

SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005

18

POST OFFICE BOX 655303

APPLICATION INFORMATION

SEPIC topology using N- and P-channel MOSFETs

The UCC39421 may also be used in the SEPIC (single-ended primary inductance converter) topology. This

topology, which is similar to the flyback, uses a capacitor to aid in energy transfer from input to output. This

configuration is shown in Figure 8. The N

moved to the other end of the inductor’s secondary winding, and a new capacitor has been placed across the

dotted ends of the two windings. The SEPIC topology offers the same advantage of the flyback in that it can

generate an output voltage that is greater or less than the input voltage.

However, it also offers improved efficiency. Although it requires an additional capacitor in the power stage, it

greatly reduces ripple current in the input capacitor and improves efficiency by transferring the energy in the

leakage inductance of the coupled inductor to the output. This also provides snubbing for the primary and

secondary windings, eliminating the need for RC snubbers. Note that the capacitor must have low ESR, with

sufficient ripple current rating for the application. Another advantage of the SEPIC is that the inductors do not

have to be on the same core.

PWM duty cycle and slope compensation

All boost and flyback converters using peak current mode control are susceptible to a phenomenon known as

subharmonic oscillation when operated in the continuous conduction mode beyond 50% duty cycle. Continuous

conduction mode (CCM) means that the inductor current never goes to zero during the switching cycle. For a

CCM boost converter, the required duty cycle for a given input and output voltage (neglecting voltage drops

across the MOSFET switches) is given by equation (7). This is shown graphically for a number of common

output voltages in Figure 9. For example, it can be seen that for a 3.3-V output (using the boost topology) slope

compensation is not required because the duty cycle never exceeds 50%.

For the flyback topology, using a coupled inductor with a 1:1 turns ratio, the duty cycle is defined by

equation (11). This is shown graphically for a number of common output voltages in Figure 10.

To prevent subharmonic oscillation beyond 50% duty cycle, a technique called slope compensation is used,

which modifies the slope of the current ramp. This is accomplished by adding a part of the timing ramp to the

current-sense input. In the UCC39421, this can be done by simply adding a resistor in series with the ISENSE

input. A current is sourced within the IC which is proportional to the internal timing ramp voltage. The value of

the resistor determines the amount of slope compensation added.

The slope compensation output current at the ISENSE pin is equal to:

I

SLOPE +

1

R

T

A

m sec

(13)

where RT is the timing resister in ohms (

Ω).

The required slope compensation resistor for a boost configuration is given by the equation:

R

SLOPE +

V

OUT *

2

V

IN min

R

SENSE

R

T

L

(14)